The escalating requirements for high performance and density associated with ultra large scale integration semiconductor devices require high speed and reliability and increased manufacturing throughput for competitiveness. Conventional practices are primarily based upon a silicon gate complementary MOS (CMOS) process, wherein a gate electrode and corresponding source and drain regions are formed by self alignment, and the withstand voltage (threshold voltage) determined by the impurity concentration level of the drain region.
Various efforts have been made in order to obtain a semiconductor with high density and a low power consumption, by increasingly reducing the gate oxide thickness and effective channel length. However, a reduced oxide thickness causes an increase in the vertical electric field effect and overlapping (parasitic) capacitance adversary affecting the delay time and power consumption of the circuits.
In order to reduce the vertical electric field effect and overlapping (parasitic) capacitance, a T-shaped gate structure is suggested by K. Kurimoto et al., IEEE 1991 IEDM Technical Digest, pp. 541-544. In the gate structure of Kurimoto et al., the thickness of both end portions of the gate insulating film is bigger than the thickness of the center portion. The thicker end portions and thinner center portion reduce the overlapping capacitance, and enable the formation of shallow source and drain extensions with a higher impurity concentration, thereby increasing the higher withstand voltage. In addition, the gate insulating film structure enables the shallow source/drain extensions to extend to the substrate underlying the end portions of the gate oxide, thereby reducing the effective channel length. Moreover, the thicker end portions reduce the hot carrier injection effect. Thus, the T-shape gate electrode provides high speed performance and high densification.
According to the semiconductor fabrication method by K. Kurimoto et al., the semiconductor device exhibiting the T-shape gate structure is formed by oxidizing the surface of a P-doped polysilicon gate electrode so as to form gate bird's beaks at both ends of the gate oxide film. However, the sidewall oxide films, formed on both sides of the gate electrode and function as a mask during the ion implantation steps to form the source and drain regions, shift the source and drain regions farther to outer positions, thereby increasing the effective channel length.
Another method of forming a T-shaped gate is disclosed in U.S. Pat. No. 5,610,430 to Yamashita et al. and illustrated in FIG. 1 to FIG. 6. In accordance with the method disclosed by Yamashita et al., as shown in FIG. 1, an oxide film 12 is formed on the surface of the semiconductor substrate 10. A polycrystalline silicon film 14 is then formed on the gate oxide film 12. Thereafter, a photoresist 16 is formed in a selected region on the polycrystalline silicon film 14. As shown in FIG. 2, portions of the polycrystalline silicon film 14 are etched by an anisotropic etching technique, thereby forming a gate electrode portion 20 and a thin film portion 22. After removing the photoresist 16, as shown in FIG. 3, a silicon nitride film 30 is deposited on the surface of the substrate 10, covering the gate electrode portion 20 and thin film portion 22. Then, as shown in FIG. 4, the thin film portion 22, a surface portion of the oxide layer 12, a silicon nitride film 30 are etched by an anisotropic etching technique, leaving a gate oxide 44 and thin oxide film 46 on the surface of the substrate 10, and the silicon nitride layer 30 on the side surfaces the gate electrode 20. As a result, the upper portion on the side surfaces of the gate electrode 20 is covered with the silicon nitride film 30 and the lower portions 42 of the side surfaces of the gate electrode 20 are exposed. Subsequently, as shown in FIG. 5, a thermal oxidation is conducted, thereby growing thermal oxide film on the exposed lower portions 42 and the thin oxide film 46. During oxidation, the exposed lower portions of the gate electrode 14 grow outwardly in a horizontal direction, thereby forming sidewall spacers combined with the silicon nitride layer film 30. Also, the exposed lower portions grow inwardly in a horizontal direction and thicker oxide portions are formed at both ends of the gate oxide 44, thereby forming, T-shaped gate electrode 40. An oxide layer 50 is also formed on the surface of the substrate 10 by oxidizing the thin oxide film portion 22. Once again, the oxide layer and the sidewall spacers are anisotropically etched in vertical direction, thereby forming the thicker sidewall spacers than the oxide layer. Then, source and drain regions 60 are formed at the surface of the semiconductor substrate 10 by ion implantation step, employing the gate electrode 14 as a mask, thereby forming shallow source/drain regions extending to the surface of the substrate 10 underlying the thicker oxide portions of the gate oxide 44, and source/drain regions formed under the oxide layer 50.
The method disclosed in Yamashita et al., however, requires complicated manufacturing steps, e.g., repeated anisotropic etching steps, e.g., to form the thin film portion 22 of the polycrystalline silicon 14, to expose the lower portions of the polycrystalline gate electrode 42, and to etch the sidewall spacers and the oxide layer 50 to the suitable thicknesses to form the source/drain regions 60 including shallow source/drain extensions by the subsequent ion implantation step. Extremely accurate controls are required during each anisotropic etching step because the doping concentration levels of the source and drain regions and shallow source/drain extensions are directly dependent to the thickness of the oxide formed by the repeated anisotropic etching steps.
For the reason identified above, there exists a need for simplified and production worthy methodology for manufacturing a semiconductor device comprising a T-shaped gate electrode.